The present invention relates to integrated circuits and, more particularly, to integrated circuits with built-in test circuitry. A major objective of the present invention is to provide enhanced validity for integrated-circuit testing.
Much of modern progress is associated with the proliferation of computer technology, which has been made possible by advances in integrated-circuit manufacturing technology. These advances have allowed smaller circuit elements. The decreasing circuit-element dimensions have allowed greater speeds (as signals have shorter distances to travel) and greater functionality (as more circuit elements are provided per integrated circuit).
Each of these advances presents a challenge. The smaller circuit elements are more vulnerable to manufacturing defects. The higher speeds require stricter timing tolerances. Greater functionality requires greater complexity, resulting in greater susceptibility to logic-design errors. Accordingly, verification of correct operation has become increasingly important.
Verification of the correct operation of integrated circuits and incorporating systems is required at many stages of development. During the design and prototype stages, verification of the correct functional operation first of system components and then of the entire system is required. During the prototype stage, verification of the correct operation within and beyond the operating region of clock frequencies, power supply voltages, and ambient temperature is required. During the production stage, verification of the correct operation of system components and the entire system to screen for manufacturing defects is required.
Testing typically involves controlling selected integrated-circuit nodes to implement test conditions and observing selected integrated-circuit nodes to determine the test results. An integrated circuit can be tested under normal conditions and during normal operation by applying test signals to its external inputs and reading the results from its external outputs. However, thoroughly testing a complex integrated circuit in this way can be unacceptably difficult and time consuming. For example, a complex series of inputs may be required to force an internal node to a desired test condition, and verification that the desired test condition has been achieved may not be feasible. Controllability and observability of internal nodes become more difficult with increasing functional distance from the external input/output ports of the integrated circuit.
Many integrated circuits provided multiplexed access to internal nodes. For example, external testing equipment can access internal nodes via a serial scan chain. Controlling and observing internal nodes using serial scan chains is generally much faster and more direct than controlling them through the normal functional blocks.
However, providing external test equipment with multiplexed access to internal nodes implies a dedicated test mode of operation that raises a concern of the validity of test data. Scanning data in and out of the integrated circuit using scan chains is typically much slower than data transfers during normal operation. In addition, the testing equipment adds loading to the monitored signals; this loading affects the operation of the electronic system being monitored. Moreover, external hardware can inject noise into the system, which can disturb system operation. To the extent test conditions fail to match normal conditions, test validity is compromised.
The problems with loading and noise can be reduced when testing is performed using onboard self-test hardware. However, the capabilities of dedicated self-test hardware are typically limited to conserve integrated circuit area and routing resources for normal functions.
The competition for circuit area and routing resources is less of a concern where testing is performed by a test program run on an onboard processor. However, the test program approach is limited to integrated circuits with suitable processors built in. In any event, a test program is often functionally distant from nodes that it needs to control and observe so that abnormally slow data rates are required for controllability and observability.
While considerable effort has been expended to make test conditions as much like normal conditions as possible, test validity is becoming more challenging. In the increasingly quantum-mechanical realm of state-of-the-art integrated-circuit devices, test validity is an inherent problem: it is a principle of quantum mechanics that the act of observing the operation of a system affects its operation.
What is needed is an approach to testability that optimizes the validity of test results. In other words, the test results should reliably indicate whether not a system would operate as intended during normal, non-test, operation. Another objective is to make high-speed monitoring possible
The present invention inverts the conventional approach to improving test validity. The conventional approach is to make test conditions more like normal operation. The present invention improves test validity by making normal operation more like test conditions. While many would balk at potentially compromising normal operation for test purposes, some surprising advantages of the invention make such a xe2x80x9ccompromisexe2x80x9d worthwhile.
The present invention provides for repeatedly sampling (xe2x80x9ccapturingxe2x80x9d) selected signals and storing the results in a queue memory. Successive samples are stored respectively at successive queue locations so that the queue represents a xe2x80x9chistoryxe2x80x9d of the captured signals over time. The queue can operate as a circular buffer so that, once the queue is full, new samples are written over the oldest stored samples. The circular buffer can be implemented in random-access-memory (RAM), with a write pointer indicating the queue location to be written to next.
The sample values for the selected signals acquired at any given time constitute a xe2x80x9ccaptured-signal vectorxe2x80x9d. Upon capture, each signal vector is stored at a respective queue location, e.g., the one pointed to by a write pointer. So that the stored signal vector is not overwritten by its immediate successor, the write pointer can be advanced as each signal vector is stored.
If the selected signals do not change from sample to sample, the queue could soon be filled with many identical vectors. The invention provides for data compression in such cases. For example, advancement of the write pointer can be inhibited when a vector matches its immediate predecessor. So that timing information is not lost, a count of the number of sample cycles over which a vector remained unchanged can be indicated by a count stored with the vector.
A more sophisticated variant of this compression scheme allows some of the selected signals to be xe2x80x9cmaskedxe2x80x9d during the comparison of successive vectors so that a vector is overwritten by its predecessor even when the values of masked signals change from vector to vector. While masking results in some loss of information, the generally great improvement in compression allows correspondingly longer histories to be represented in the queue.
The queue can be used, not only for storing captured-signal vectors, but also for storing drive-signal vectors. Preferably, the queue can transmit drive-signal vectors and store captured-signal vectors concurrently. To this end, the queue can be a dual-ported RAM with separately addressable read and write functions. If race conditions are not a concern, a single read/write pointer can be used. If race conditions are a concern, the current read and write locations can be forced to be different-either with a single pointer with an offset between read and write locations, or using restrictions on the pointers to ensure they do not point to the same location.
In a test-setup mode, a tester, e.g, external test equipment and/or a test program, can write drive-signal vectors to the queue via a test port. Then, in test-drive mode, the test-drive-signal vectors are sequentially transmitted to selected driven-signal nodes. During test-drive mode, captured-signal vectors are stored in the queue. Finally, in a test-readout mode, the contents of the queue can be read via the test port.
During test-setup mode and test-readout mode, data can be transferred between the queue and the tester via a test port. The data transfer rate can be dropped as necessary to accommodate the tester""s capabilities and the available bandwidth between the queue and the tester. While the speeds and other conditions during test-setup mode and test-readout mode can be very different from normal operation, test results are not determined during these modes.
Tests results are determined during test-drive mode. In test-drive mode, the observability function, i.e., the storing of captured-signal vectors, is the same as it is for normal operation. Thus, a major advantage of the present invention is that, insofar as the observability function is concerned, testing does not deviate from normal operation. Test validity is correspondingly enhanced.
A surprising additional advantage is that useful test data can be obtained without the controllability function causing a deviation from normal operation. Normal operation can be halted at any time so that the queue contents can be read (in test-readout mode). The data so read is collected during normal operation, without any distortion due to testing. The data represents a recent history of normal operation that can be analyzed to characterize system performance. This system-history analysis has enhanced validity because the underlying data does not reflect any deviations form normal operation. These and additional features and advantages of the invention are apparent from the detailed description below with reference to the following drawings.